https://jjcit.org/paper/164 10.5455/jjcit.71-1644147942 Rajesh Khatri,D. K. Mishra CMOS,UWB,Noise figure,IIP3,Receiver front end 1 7260 1522 6-Feb.-2022 22-Mar.-2022 13-Apr.-2022 This paper proposes a novel and fully optimized ultra-wideband RF receiver front end in UMC 180nm 1P6M CMOS process. The heterodyne architecture used in this work does not use the on-chip image reject mixer. The proposed receiver consists of a cascode inductively degenerated common source differential low noise amplifier and a folded Gilbert down-conversion mixer. The differential low-noise amplifier eliminates the use of active balun and improves the noise performance, while the folded architecture reduces the power dissipation of the receiver. The post-layout simulated result shows that the receiver has a voltage gain of 15.2 - 19.8dB, a noise figure of 4.8 - 8.9dB, a third-order input intercept point (IIP3) of -6.3 to -2.9dBm and consumes 31.5mW from a 1.8V supply. The receiver has a good reverse isolation S12 of -42 to -59dB due to cascode configuration and occupies an area of 2.55mm2.